Course Description

This course provides a complete theoretical understanding of SoC (System-on-Chip) Functional Verification, covering every essential concept used in real semiconductor companies.
It is designed for students, freshers, and verification engineers who want to clearly understand how IPs combine into an SoC, how verification is done at system-level, how C and UVM environments interact, and how real chips boot and execute tests.

The course focuses on practical industry workflows explained in a simplified and structured way, without diving into tool-level execution. By the end of the course, learners will develop strong familiarity and confidence in SoC-level verification.

What You Will Learn

What is an SOC?

Definition of SoC

Components: CPU, Interconnect, Memories, DMA, Peripherals, Debug logic, Boot ROM

Why SoC verification is more complex than IP-level verification

IP vs Sub-System vs SOC

IP Level: Single protocol (APB, AXI, QSPI, SPI, UART) verification

Subsystem Level: Combination of 2–5 IPs + interconnect + basic software

SOC Level: Complete chip with CPU + buses + boot flow + C test execution

Reuse of verification components from IP to SOC

Verification at SOC Level

Functional verification in CPU-driven environment

HW–SW integration challenges

Debugging SoC issues (ROM boot, memory map, address decoding)

Achieving coverage closure at SoC

SOC Testbench Architecture

SystemVerilog + UVM + C test integration

Bus Functional Models (BFMs) vs VIPs

UVM components (env, agents, sequences, scoreboard) at SOC context

Top-level DUT connections and SoC-level interfaces

Reusing VIP from IP verification

VIP Integration at SOC Level

How agents master/monitor traffic

Integrating custom VIPs (QSPI, I2C, JTAG, etc.)

HW–SW Co-Verification (Bare Metal Environment)

Interaction of C functions with RTL

Software-driven verification

SoC memory map usage

Testing peripherals using CPU instructions

UART prints, memory polling, interrupts

SOC Booting Process

Init sequence

Boot ROM execution

Clock and power initialization

Peripheral initialization

Application code loading

Execution of testcases via CPU

C and SV-UVM Testcase Build + Run Flow

How C code is compiled (C → .o → .elf → .hex)

Loading ROM/RAM images into the simulator

Linking C testcases with UVM environment

Starting sequences + C execution in parallel

Checking results using UVM scoreboards and C logs

Learning Outcome

By the end of the training, you will clearly understand:

✔ How real SoCs are verified in companies
✔ How IP verification differs from SoC verification
✔ How to integrate IPs, VIPs, and C tests in a single environment
✔ How CPU, memories, buses, and peripherals work together
✔ How bare-metal tests and UVM interact
✔ Real SoC boot and test execution sequence

This gives you solid conceptual clarity even without hands-on work.

⚠ Disclaimer

This course is intended for educational and learning purposes only.
It provides theoretical explanations of SoC Functional Verification concepts and does NOT include any hands-on practicals, tool usage, simulations, code execution, implementation, or project-level guidance.

The information shared in this course is general, conceptual, and high-level, and is not tailored for any specific company, project, client environment, or commercial application.

While every effort is made to explain concepts accurately,
the instructor and the course are not responsible or liable for how learners choose to apply (or misapply) this knowledge in real-world, client, company, or commercial projects.

Who Should Attend?

Students preparing for VLSI DV roles

IP-level DV engineers moving to SoC-level verification

Anyone preparing for SoC DV interviews

Freshers who want a complete SoC overview