🧭 Course Title

SPI Core/Controller Verification using UVM, RAL, and Virtual Sequences

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🎯 Course Overview

This 4–5 week, industry-oriented training program focuses on verifying a pre-existing SPI Core using SystemVerilog UVM methodology. Students will learn to develop a complete UVM-based verification environment — from requirement analysis to full regression automation — mirroring real-world verification workflows used in leading semiconductor companies.

Rather than designing RTL, the program exclusively targets testbench creation, functional coverage, assertions, and RAL-based verification of an SPI core integrated with an Wishbone interface.

By the end of the course, students will independently build and execute a full verification project — complete with UVM components, coverage reports, virtual sequences, and automated regressions.

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⚙️ Key Learning Outcomes

Participants will:

Understand and analyze SPI and Wishbone specifications for verification requirements.

Create a detailed Verification & Test Plan including coverage and assertions.

Develop a complete UVM testbench with reusable components (Driver, Monitor, Sequencer, Agent, Environment).

Implement Virtual Sequencer and Virtual Sequences for multi-agent coordination.

Build and use a Register Abstraction Layer (RAL) for register-level verification.

Add functional coverage and protocol assertions to ensure verification completeness.

Automate regressions using Makefile and TCL scripts.

Debug simulation issues using logs and waveform analysis tools.