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Instructor: MohammadLanguage: ENGLISH
Unit 0: Introduction to the course.
● Understand the course prerequisite and outcome.
●Introduction to protocol.
●Why do we need protocol?
Unit 1: Protocol Basics
●Protocol Difference.
●On chip/Off-chip protocol.
Unit 2: USB
●Why USB?
●USB Hierarchy.
●USB cable types.
●How did USB evolve?
●What is latest in USB.
●USB data rates.
Unit 3: USB 2.0 Protocol Layer
●USB Bus speed. (LS/FS/HS speed)
●USB 2.0 Features.
●Device Detection.
●Speed Negotiation.
●Enumeration.
●What are Endpoints and descriptors?
●Descriptor types.
Unit 4: USB 2.0 Packet Types
●Token Packet.
●SOF Token.
●Data Packet.
●Handshake Packet.
●Special Packet.
●Packet structure Waveforms.
●Sync, PID, ADDR, ENDP, CRC, EOP.
●Endpoint Types.
Unit 5: USB 2.0 Transfer Types
●Non-Periodic Transfer.
●Periodic Transfer.
●Control, Bulk, Interrupt, Isochronous Transfers.
Unit 6: USB 2.0 SPLIT Transfer
●USB Hub Specifications.
●Hub config.
●Split transfers.
Unit 7: 2.0 Link Power Management (LPM)
●Reason of Link Power Management (LPM).
●Issue with existing Suspend/Resume.
●LPM State and PID.
●USB 2.0 LPM Extension Transaction.
●Protocol Extension Token.
●LPM Transaction.
Unit 8: USB 2.0 PHY types (UTMI)
●Types of PHY’s (UTMI, ULPI, HSIC, edp/edm).
●UTMI signal description.
●Getting started with the PHY interface.
Project 1 (Testbench Development to verify PHY RTL)
Code industry standard Verification Environment as below Infrastructure.
●Testbench for UTMI PHY.
●Understand how SerDes, NRZI, Bit Stuff etc.
●Signal level understanding.
Project 2 (Testbench Development for USB Device Core RTL)
Code standard Verification Environment for device rtl.
●Standard Testbench.
●Utmi-to-Utmi Testbench config with PHY.
●Utmi-to-Utmi Testbench config. [TBD]
●D+/D- Testbench config. [TBD]
●Sub-System setup with PHY integration. [TBD]
●Develop a USB_HOST model in System Verilog and hook it to the device RTL. [Live Coding]
📞 Contact Details:
Chandan - 8310757916
Momammed Khan- 8876833813
contact@elobchip.com
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