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DDR3 & DDR4 JDEC specification
JESD79-3F (1)
490456868-JESD79-4-DDR4-SDRAM-STANDARD (1)
DDR5 Spec JESD79-5 (1)
AMBA AXI useful in DDR and PCIE
DDR Coding flow and Interview Explanation
DDR Versions, DRAM size.
ddr_training_day1 (1)
ddr_visual_diagrams
DRAM Addressing table discussion
ddr_day2_comprehensive
DRAM Addressing Table part2
ddr_day3_notes
DRAM Address and DATA transfer
ddr_class4_notes (1)
DDR3 Command truth table JDEC
ddr_day5_notes
DDR Clk and Clk# signals explanation
ddr_complete_guide
RAS#,CAS#,WE#,CS#, Reset# signals in dram
ddr_day7_control_signals (1)
DDR EEPROM Needs
day8_sdram_complete
Command truth table Act, write, read jdecc
Normal Write and read operation
Ddr quiz-01
DDR DIMM
BL8, BC4 and fixed BL8 or BC4 and on the fly(OTF)
DDR Ranks, Channels in DRAM
DDR4 Signals, DDR4 Address table, DDR4 Command truth table JDECC
MR0, DDR3 Timing parameters Basics
DDR3 Timing parameters CAS, CWL, TRCD,TRP,TRAS,TCCD
Tool installation, Revision of previous classes
Reset and Initialization for ddr3
Reset and Initialization for ddr3 part2
DRAM coding side explanation
memory_model
interface
Dram coding interface conclusion
DRAM Full timing diagram for ddr3-1600
DRAM Timing diagram
Full timing diagram with values
DDR4 Timing parameters
DDR4 Timing parameters JDEC
SIMM,DIMM,UDIMM&RDIMM
RDIMM, RCD, SODIMM, LRDIMM JDEC
MR0, DDR3 JDEC SPEC
MR0, Burst Types discussion
DLL Block in DRAM
MR0 & MR3 DDR3
MR3 & MPR DDR3 & DDR4 JDDEC
DDR ODT(On Die Termination)
ZQ calibration DDR
MR1 DDR3 & DDR4
DMA & RMW DDR3 & DDR4
MR2, TDQS, Self Refresh
Refresh, Bit line, Word line, Sense amplifier , self refresh DDR
DDR5 Transaction flow
DDR5 Coding Meeting
DDR5 final dram transaction flow